Computer emulators have been around almost as long as digital computers themselves. The usual approach was to write a computer program to make the computer "think" that it was the thing being emulated and then make the computer run accordingly. When the thing being emulated is extremely complex, such as an electronic communications switch, writing an emulation program can be extremely difficult considering the requirements of real-time processing. When writing a program to emulate how the switch would interact with one of its printed circuit (PC) cards, in order to test that card, it is necessary that the testing program make the card or unit under test (UUT) think that it is actually a part of the switch (or other massive system). The cost of writing anew the test program for each different type of PC card that is used in the switch can be prohibitive.
There have been several efforts to make computerized testing devices more adaptable and less expensive to program by dividing them into two parts, with the first part being of a more generalized nature to perform the more elementary tasks and signal processing functions. Then, the second part of the testing device comprises interchangeable adapters each of which is constructed specifically to adapt the output of the first part to the specific requirements of the UUT.
U.S. Pat. No. 4,622,647, granted on Nov. 11, 1986, to Sagnard, et al. discloses a computerized system for testing a microprocessor-equipped printed circuit card. There is a standard base unit which has various components interconnected by a multi-bus. The bus serves interface units, the outputs of which are connected by cables to a specific intermediate unit. The intermediate unit has several multi-busses and is specific to the type of printed circuit card to be tested.
Therefore, the intermediate unit links the standard base unit to the circuit card under test. Grippers on the intermediate unit are used to apply pseudo or faked microprocessor signals to the microprocessor itself or to the rest of the circuitry on the PC card under test to see how they perform. Similarly, a plug replaces the ROM of the unit under test (the printed circuit card) and provides ROM pseudo outputs to the rest of the circuitry.
U.S. Pat. No. 4,807,161, granted on Feb. 21, 1989, to Comfort, et al. discloses an automatic testing system in which a computerized tester has a main system bus which is connected through a buffer to a backplane I/O bus. A complete, microcomputer testing system is then built around that main system bus, which links all of the testing system's peripherals.
The main or fixed computerized portion of the testing system includes the power supplies. The variable part of the test set is optional to suit the specific test to be made. The variable part of the test set is connected to the main part of the test set by sheet cables and the plugs thereof.
The patent describes a bed-of-nails probe connection to the nodes of the specific circuit under test. There is a probe interface as well as a relay matrix to control the nature and timing of the use of those probes.
The test set can be used to test the rest of a microprocessor board by emulating and thus replacing the microprocessor.
The microcomputer that runs the test set can be used by an operator to apply different stimuli and signal waveforms to the circuit or unit under test, using the microcomputer's monitor and keyboard.
There is a buffering and timing circuit (POD) connected between the UUT and the computerized tester, that appears to be placed there to adapt the signals and timing of the tester to the UUT.
Both of these patents disclose systems in which the same computer handles the all aspects of the test set, including storage of the several test programs and processes the generation of the test conditions and determine if the unit under test passes the functional test.
In order to test a different type of product, not only must the computer load a different test program into its random access memory (RAM) but the interface to the UUT must physically be changed, i.e., the interface to the prior type of product must be unplugged and a different physical interface must be plugged in its place.
The host computer of both of these patents must generate the data needed to emulate the environment of the UUT, eg., generate a series of test conditions to feed to the UUT, and then analyze the response,if any, from the UUT.
For example, in a typical test-set computer, it may be necessary to generate a waveform of a particular shape, amplitude, and wavelength. If this is not done in real time (while the test is in process), the digital representation of the wave pattern must be generated before the test and then stored in the memory of the actual test set. If the host computer and the test set are separate and connected with a data link, the transmission of the digital representation of the waveform can inordinately tie up the host computer and the data link and thus slow the process of testing.
If a pattern is generated by the computer in real time, this may be too much to demand of a typical host computer that might be used with a test set. Such a host computer could have a processor that may not be manufactured primarily for and optimized for digital signal generation. Similarly, if the response from the UUT is complex, such as when the response is a data stream that must be analyzed, the typical host computer is further burdened by the need also to analyze that data stream from the UUT.